In a semiconductor circuitry, latchup is caused by current flowing from a substrate injection source within a guarding structure to adjacent circuitry where parasitic p-n-p-n structure exists. An example of such a parasitic p-n-p-n structure is a CMOS inverter that employs a PFET and an NFET connected in series. To prevent current from I/O drivers into adjacent circuitry, guard rings are placed around I/O circuitry.
Examination of a typical CMOS circuitry shows the origin of the latchup mechanism. PFETs are built in an n-well formed within a P− substrate and NFETs are built in the P− substrate and outside the n-well. The drains of the PFETs and the n-well are both biased with a positive voltage supply, VDD, while the source of the NFETs and the P− substrate are both connected to a negative power supply, VSS. The negative power supply VSS is often a connection to ground. Between a neighboring pair of a PFET and an NFET, as can be found in a CMOS inverter for example, a parasitic p-n-p-n structure exists between the VDD supply and the VSS power supply formed by the PFET drain, the n-well, the P-substrate, and the NFET source due to their nature as doped semiconductor regions.
This parasitic p-n-p-n structure can be approximated to first order with an equivalent circuit comprising one pnp bipolar transistor, one npn bipolar transistor, and two resistors, wherein the base of the pnp bipolar transistor and the collector of the npn bipolar transistor share the same n-well, and the pnp bipolar transistor and the base of the npn bipolar transistor share the P− substrate. The n-well and P− substrate are both collectors and bases at the same time. In an equivalent circuit approximation, an upper shunt resistor in a parallel connection between the VDD power supply and the base of the pnp bipolar transistor approximates the resistance. This resistance is associated with the resistance between the n-well contact and a p-type device contained within an n-well. Similarly, a lower shunt resistor in a parallel connection between the base of the npn bipolar transistor and the VSS power supply approximates the resistance between the two components. This resistance is associated with the resistance between the p+substrate contact and an n-type device within the substrate. Forward biasing of the parasitic pnp and the npn transistors can lead to a S-type I-V characteristic and turn-on of the pnpn structure. This condition is called “latchup.” Latchup should be avoided in semiconductor circuits since it can cause semiconductor chip failure. Reference is herein made to Ker et al., “Automatic Methodology for Placing the Guard Rings into Chip layout to Prevent Latchup in CMOS IC's,” IEDM Tech. Dig., 2001, pp. 113-116, which shows an equivalent circuit for the parasitic components of a pnpn structure in FIG. 1(b) for illustration.
Guard rings are utilized to prevent a latchup by improving “internal latchup” and “external latchup” robustness in semiconductor structures and chips. Guard rings are any physical region or shape that improves the latchup robustness of a structure, circuit or chip.
To prevent an internal latchup, guard rings are placed between the pnp and the npn parasitic transistors to electrically de-couple the two parasitic transistors to avoid a regenerative feedback. Guard rings can be reverse biased PN junction diodes placed between the conduction paths of the parasitic p-n-p-n structures. Typically, guard rings consist of connections to both the VSS power supply and the VDD power supply A grounded guard ring is formed by a low-resistance P+ area that connects to VSS power supply. A power supply guard ring is formed by an n-well and an N+ region on the substrate that connects to the VDD power supply.
To prevent an external latchup, guard rings are placed between one sector of a structure, circuit or chip to another sector of a structure, circuit or chip to avoid injection across the sectors. Guard rings can consist of isolation regions or doped regions. In the case of doped regions, these guard rings are biased to a power supply to collect minority carriers injected into a region. When an injection source is present, and the role of the guard ring is to prevent the injection of minority carriers from reaching other regions of the semiconductor chip. In an external latchup condition, the injected minority carriers serve as a virtual external injection source to a region where a p-n-p-n structure exists. For an external latchup guard ring region to be effective, it is important to allow the collection of the extra injected carriers in the substrate to prevent them from reaching the sensitive regions of the semiconductor chip. In this scenario, the resistance of the guard ring must be low enough to allow the collection of large currents without losing its effectiveness. When the voltage drop within the guard ring itself is significant, it can not “sink” the external current from the injection region.
The effectiveness of a guard ring is dependent upon many variables including the following: the width of the guard ring, the depth of the guard ring, the sheet resistance of the guard ring (which is dependent upon the implant conditions), spacing between the injection sources and the guard ring, and substrate doping concentration. If the guard ring resistance itself is high, this can lead to a voltage drop within the guard ring and de-bias the guard ring. The parameters that affect the resistance of the guard ring includes species and dose of the dopants implanted into the guard ring, dopant activation during anneals, the dimensions (width and depth) of the guard ring, the density of guard ring contacts, the resistance of each guard ring contact, the thickness and resistance of silicide film forming contacts, and the metal bus resistance to the VDD power supply grid and to the VSS power supply grid (or the ground grid).
With the continual scaling of semiconductor devices and with a limited number of I/O pads in present day IC'is, the guard ring resistance has increased to make the guard ring structures less effective. The problem is that reduced guard ring width, reduced contact density (limited by bussing and manufacturing polish limits), and limitations on the bus location introduce a series resistance with the parasitic lateral npn bipolar transistor formed between an injection source and the guard ring.
As current flows from an injection source in a latchup condition such as an ESD event, the role of the guard ring is to collect the excess current and avoid the current flowing to other chip sectors which may be sensitive to CMOS latchup (e.g. array regions with dense CMOS circuits). As the series resistance increases with the guard ring itself (e.g. which is serving as a npn collector), the biasing of the parasitic lateral npn bipolar transistor is decreased. When the resistance is significant, the lateral bipolar is de-biased leading to the carriers traveling to other locations within the semiconductor chip which may be sensitive to CMOS latchup (e.g. core regions of dense CMOS circuitry, ASIC gate array, etc). However, the role of the guard ring is to prevent injection of minority carriers into other chip regions. Any design or process features that compromise the effectiveness will impact the external guard ring effectiveness of fulfilling this objective and function. Other factors also affect the effectiveness of guard ring structures in preventing a latchup in IC circuits with small device dimensions. These factors include contact density, guard ring resistance, bus resistance, and injection source location dependency. The design parameters between the point of the injection of minority carriers and the power supply influence the ability of the guard ring to “sink” the injection current.
Latchup testing in a CMOS circuit is typically performed by injecting a trigger current of +/−100 mA on the I/O pins to insure that latchup is not triggered under such conditions. Traditionally, guard rings are then manually placed as needed to prevent a latchup. Also, some automated processes of placing guard rings have been known in the art. One such example is shown in Ker et al., “Automatic Methodology for Placing the Guard Rings into Chip layout to Prevent Latchup in CMOS IC's,” IEDM Tech. Dig., 2001, pp. 113-116, wherein the guard rings are automatically placed around the power buses. While such automatic placement of guard rings tend to insure that sufficient level of protection against latchup is present in an IC, the large area that such guard ring structures occupy make the design layout less effective in the use of the semiconductor area.
Due to the general degradation of the effectiveness of the guard rings, neither manual placement of guard rings nor automatic placement of guard rings based on the availability of power bus is sufficient to achieve a high level of latchup protection with a minimum semiconductor space usage. Manual placement of guard rings, which tend to be area-effective, is prone to missing some the complexities affecting the effectiveness of guard rings as well as being time-consuming. Automatic placement of the guard rings based on the availability of power buses nearby tend to place more than enough guard rings thus use more semiconductor area than necessary to provide sufficiently high level of latchup protection.
Therefore, there exists a need for a methodology for automatically placing guard rings in a more area-efficient yet effective way.
There exists another need to control the guard ring to power supply path resistance between any injection source (e.g. electrostatic discharge (ESD) device, diffusion, or external ionizing radiation region) and the guard ring region.
There exists yet another need to provide an alternate design option when the guard ring to power supply path resistance exceeds a preset limit.